In conventional nonvolatile semiconductor memory devices (memories), device elements are integrated in a two-dimensional plane on a silicon substrate. To increase the storage capacity of a memory, the dimension of one element is reduced (miniaturized). However, such miniaturization has recently become difficult in terms of cost and technology.
In this context, a collectively processed three-dimensional stacked memory has been proposed. The collectively processed three-dimensional stacked memory includes a stacked body with insulating films and electrode films alternately stacked therein, silicon pillars piercing the stacked body, and a charge storage layer (memory layer) provided between the silicon pillar and the electrode film. Thus, a memory cell is provided at the intersection of the silicon pillar and each electrode film.
Furthermore, JP-A 2009-146954, for example, proposes a technique for three-dimensionally arranging memory cells. In this technique, memory holes are formed in a stacked body in which a plurality of word electrode layers each functioning as a control gate in a memory cell are alternately stacked with insulating layers. A charge storage film is formed on the inner wall of the memory hole. Then, silicon is provided in the memory hole. Furthermore, JP-A 2009-146954 discloses a data erasing method specific to such a three-dimensional stacked memory. This erasing method is based on the Gate Induced Drain Leakage (GIDL) current.